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features ? high-performance, low-power avr ? 8-bit microcontroller advanced risc architecture ? 131 powerful instructions ? most single-clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 20 mips throughput at 20 mhz ? on-chip 2-cycle multiplier nonvolatile program and data memories ? 64k bytes of in-system self-programmable flash endurance: 10,000 write/erase cycles ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-w rite operation ? 2k bytes eeprom endurance: 100,000 write/erase cycles ? 4k bytes internal sram ? programming lock for software security jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities a ccording to the jtag standard ? extensive on-chip debug support ? programming of flas h, eeprom, fuses, and lock bits through the jtag interface peripheral features ? two 8-bit timer/counte rs with separate prescalers and compare modes ? one 16-bit timer/counter with separate prescaler, compare mode, and capture mode ? real time counter with separate oscillator ? six pwm channels ? 8-channel, 10-bit adc differential mode with selectable gain at 1x, 10x or 200x ? byte-oriented two-wire serial interface ? one programmable serial usart ? master/slave spi serial interface ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? interrupt and wake-up on pin change special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated rc oscillator ? external and internal interrupt sources ? six sleep modes: idle, adc noise reduc tion, power-save, power-down, standby and extended standby i/o and packages ? 32 programmable i/o lines ? 40-pin pdip, 44-lead tqfp, and 44-pad qfn/mlf speed grades ? ATMEGA644v: 0 - 4mhz @ 1.8 - 5.5v, 0 - 10mhz @ 2.7 - 5.5v ? ATMEGA644: 0 - 10mhz @ 2.7 - 5.5v, 0 - 20mhz @ 4.5 - 5.5v power consumption at 1 mhz, 3v, 25 c for ATMEGA644 ? active: 240 a @ 1.8v, 1mhz ? power-down mode: 0.1 a @ 1.8v 8-bit microcontroller with 64k bytes in-system programmable flash ATMEGA644/v preliminary summary 2593ls?avr?02/07
2 2593ls?avr?02/07 ATMEGA644 1. pin configurations figure 1-1. pinout ATMEGA644 note: the large center pad underneath the qfn/ mlf package should be soldered to ground on the board to ensure good mechanical stability. (pcint8/xck0/t0) pb0 (pcint9/clko/t1) pb1 (pcint10/int2/ain0) pb2 (pcint11/oc0a/ain1) pb3 (pcint12/oc0b/ss) pb4 (pcint13/mosi) pb5 (pcint14/miso) pb6 (pcint15/sck) pb7 reset vcc gnd xtal2 xtal1 (pcint24/rxd0) pd0 (pcint25/txd0) pd1 (pcint26/int0) pd2 (pcint27/int1) pd3 (pcint28/oc1b) pd4 (pcint29/oc1a) pd5 (pcint30/oc2b/icp) pd6 pa0 (adc0/pcint0) pa1 (adc1/pcint1) pa2 (adc2/pcint2) pa3 (adc3/pcint3) pa4 (adc4/pcint4) pa5 (adc5/pcint5) pa6 (adc6/pcint6) pa7 (adc7/pcint7) aref gnd avcc pc7 (tosc2/pcint23) pc6 (tosc1/pcint22) pc5 (tdi/pcint21) pc4 (tdo/pcint20) pc3 (tms/pcint19) pc2 (tck/pcint18) pc1 (sda/pcint17) pc0 (scl/pcint16) pd7 (oc2a/pcint31) pa4 (adc4/pcint4) pa5 (adc5/pcint5) pa6 (adc6/pcint6) pa7 (adc7/pcint7) aref gnd avcc pc7 (tosc2/pcint23) pc6 (tosc1/pcint22) pc5 (tdi/pcint21) pc4 (tdo/pcint20) (pcint13/mosi) pb5 (pcint14/miso) pb6 (pcint15/sck) pb7 reset vcc gnd xtal2 xtal1 (pcint24/rxd0) pd0 (pcint25/txd0) pd1 (pcint26/int0) pd2 (pcint27/int1) pd3 (pcint28/oc1b) pd4 (pcint29/oc1a) pd5 (pcint30/oc2b/icp) pd6 (pcint31/oc2a) pd7 vcc gnd (pcint16/scl) pc0 (pcint17/sda) pc1 (pcint18/tck) pc2 (pcint19/tms) pc3 pb4 (ss/oc0b/pcint12) pb3 (ain1/oc0a/pcint11) pb2 (ain0/int2/pcint10) pb1 (t1/clko/pcint9) pb0 (xck0/t0/pcint8) gnd vcc pa0 (adc0/pcint0) pa1 (adc1/pcint1) pa2 (adc2/pcint2) pa3 (adc3/pcint3) pdip tqfp/qfn/mlf
3 2593ls?avr?02/07 ATMEGA644 1.1 disclaimer typical values contained in this datasheet ar e based on simulations and characterization of other avr microcontrollers manufactured on the same process technology. min and max values will be available after the device is characterized. 2. overview the ATMEGA644 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the ATMEGA644 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. 2.1 block diagram figure 2-1. block diagram cpu gnd vcc reset power supervision por / bod & reset watchdog oscillator watchdog timer oscillator circuits / clock generation xtal1 xtal2 port a (8) port d (8) pd7..0 port c (8) pc7..0 twi spi eeprom jtag 8bit t/c 0 8bit t/c 2 16bit t/c 1 sram flash usart 0 internal bandgap reference analog comparator a/d converter pa7..0 port b (8) pb7..0
4 2593ls?avr?02/07 ATMEGA644 the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. the ATMEGA644 provides the following features: 64k bytes of in-system programmable flash with read-while-write capabilitie s, 2k bytes eeprom, 4k bytes sram, 32 general purpose i/o lines, 32 general purpose working registers, real time counter (rtc), three flexible timer/counters with compare modes and pwm, 2 u sarts, a byte oriented 2-wire serial inter- face, a 8-channel, 10-bit adc with optional di fferential input stage with programmable gain, programmable watchdog timer with internal oscillator, an spi serial port, ieee std. 1149.1 compliant jtag test interface, also used fo r accessing the on-chip debug system and program- ming and six software selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi port, and interrupt system to continue functioning. the power-down mode saves the regist er contents but free zes the oscillator, di sabling all other chip functions until the next interrupt or hardware reset. in power-save mode, the asynchronous timer continues to run, allowing the user to main tain a timer base while the rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o modules except asynchro- nous timer and adc, to minimize switching no ise during adc conversions. in standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. this allows very fast start-up combined with low power consumption. in extended standby mode, both the main oscillator and th e asynchronous timer continue to run. the device is manufactured using atmel?s high- density nonvolatile memory technology. the on- chip isp flash allows the prog ram memory to be repr ogrammed in-system th rough an spi serial interface, by a conventional nonvolatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the applicatio n flash memory. software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel ATMEGA644 is a powerful microcontroller that provides a highly flexible and cost effec- tive solution to many embedded control applications. the ATMEGA644 avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 2.2 pin descriptions 2.2.1 vcc digital supply voltage. 2.2.2 gnd ground. 2.2.3 port a (pa7:pa0) port a serves as analog inputs to the analog-to-digital converter. port a also serves as an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port a output buffers have symmetr ical drive characterist ics with both high sink
5 2593ls?avr?02/07 ATMEGA644 and source capability. as inputs, port a pins that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the ATMEGA644 as listed on page 76 . 2.2.4 port b (pb7:pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the ATMEGA644 as listed on page 78 . 2.2.5 port c (pc7:pc0) port c is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port c output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port c pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port c also serves the functions of the jtag interface, along with special features of the ATMEGA644 as listed on page 81 . 2.2.6 port d (pd7:pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port d pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various sp ecial features of the ATMEGA644 as listed on page 83 . 2.2.7 reset reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 9-1 on page 47 . shorter pulses are not guaranteed to generate a reset. 2.2.8 xtal1 input to the inverting oscillato r amplifier and input to the in ternal clock operating circuit. 2.2.9 xtal2 output from the invert ing oscillator amplifier.
6 2593ls?avr?02/07 ATMEGA644 2.2.10 avcc avcc is the supply voltage pin for port f and the a nalog-to-digital converter. it should be exter- nally connected to v cc , even if the adc is not used. if the adc is used, it should be connected to v cc through a low-pass filter. 2.2.11 aref this is the analog reference pin for the analog-to-digital converter. 3. resources a comprehensive set of development tools, application notes and datasheetsare available for download on http:// www.atmel.com/avr.
7 2593ls?avr?02/07 ATMEGA644 4. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved - - - - - - - (0xfe) reserved - - - - - - - - (0xfd) reserved - - - - - - - - (0xfc) reserved - - - - - - - - (0xfb) reserved - - - - - - - (0xfa) reserved - - - - - - - - (0xf9) reserved - - - - - - - (0xf8) reserved - - - - - - - - (0xf7) reserved - - - - - - - - (0xf6) reserved - - - - - - - - (0xf5) reserved - - - - - - - (0xf4) reserved - - - - - - - - (0xf3) reserved - - - - - - - - (0xf2) reserved - - - - - - - - (0xf1) reserved - - - - - - - (0xf0) reserved - - - - - - - - (0xef) reserved - - - - - - - (0xee) reserved - - - - - - - - (0xed) reserved - - - - - - - - (0xec) reserved - - - - - - - - (0xeb) reserved - - - - - - - (0xea) reserved - - - - - - - - (0xe9) reserved - - - - - - - - (0xe8) reserved - - - - - - - - (0xe7) reserved - - - - - - - (0xe6) reserved - - - - - - - - (0xe5) reserved - - - - - - - - (0xe4) reserved - - - - - - - - (0xe3) reserved - - - - - - - (0xe2) reserved - - - - - - - - (0xe1) reserved - - - - - - - (0xe0) reserved - - - - - - - (0xdf) reserved - - - - - - - - (0xde) reserved - - - - - - - - (0xdd) reserved - - - - - - - - (0xdc) reserved - - - - - - - (0xdb) reserved - - - - - - - - (0xda) reserved - - - - - - - - (0xd9) reserved - - - - - - - - (0xd8) reserved - - - - - - - - (0xd7) reserved - - - - - - - - (0xd6) reserved - - - - - - - - (0xd5) reserved - - - - - - - - (0xd4) reserved - - - - - - - - (0xd3) reserved - - - - - - - - (0xd2) reserved - - - - - - - - (0xd1) reserved - - - - - - - - (0xd0) reserved - - - - - - - - (0xcf) reserved - - - - - - - - (0xce) reserved - - - - - - - - (0xcd) reserved - - - - - - - - (0xcc) reserved - - - - - - - - (0xcb) reserved - - - - - - - - (0xca) reserved - - - - - - - - (0xc9) reserved - - - - - - - - (0xc8) reserved - - - - - - - - (0xc7) reserved - - - - - - - - (0xc6) udr0 usart0 i/o data register 181 (0xc5) ubrr0h - - - - usart0 baud rate register high byte 186/198 (0xc4) ubrr0l usart0 baud rate register low byte 186/198 (0xc3) reserved - - - - - - - - (0xc2) ucsr0c umsel01 umsel00 upm01 upm 00 usbs0 ucsz01 ucsz00 ucpol0 184/197 (0xc1) ucsr0b rxcie0 txcie0 udrie0 rxe n0 txen0 ucsz02 rxb80 txb80 183/197 (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 182/196
8 2593ls?avr?02/07 ATMEGA644 (0xbf) reserved - - - - - - - - (0xbe) reserved - - - - - - - - (0xbd) twamr twam6 twam5 twam4 twam3 twam2 twam1 twam0 -229 (0xbc) twcr twint twea twsta twsto twwc twen -twie 225 (0xbb) twdr 2-wire serial interface data register 227 (0xba) twar twa6 twa5 twa4 tw a3 twa2 twa1 twa0 twgce 229 (0xb9) twsr tws7 tw s6 tws5 tws4 tws3 - twps1 twps0 227 (0xb8) twbr 2-wire serial interface bit rate register 225 (0xb7) reserved - - - - - - - - (0xb6) assr - exclk as2 tcn2ub ocr2aub ocr2bub tcr2aub tcr2bub 150 (0xb5) reserved - - - - - - - - (0xb4) ocr2b timer/counter2 output compare register b 149 (0xb3) ocr2a timer/counter2 output compare register a 149 (0xb2) tcnt2 timer/counter2 (8 bit) 149 (0xb1) tccr2b foc2a foc2b - - wgm22 cs22 cs21 cs20 148 (0xb0) tccr2a com2a1 com2a0 com2b1 com2b0 - - wgm21 wgm20 145 (0xaf) reserved - - - - - - - - (0xae) reserved - - - - - - - - (0xad) reserved - - - - - - - - (0xac) reserved - - - - - - - - (0xab) reserved - - - - - - - - (0xaa) reserved - - - - - - - - (0xa9) reserved - - - - - - - - (0xa8) reserved - - - - - - - - (0xa7) reserved - - - - - - - - (0xa6) reserved - - - - - - - - (0xa5) reserved - - - - - - - - (0xa4) reserved - - - - - - - - (0xa3) reserved - - - - - - - - (0xa2) reserved - - - - - - - - (0xa1) reserved - - - - - - - - (0xa0) reserved - - - - - - - - (0x9f) reserved - - - - - - - - (0x9e) reserved - - - - - - - - (0x9d) reserved - - - - - - - - (0x9c) reserved - - - - - - - - (0x9b) reserved - - - - - - - - (0x9a) reserved - - - - - - - - (0x99) reserved - - - - - - - - (0x98) reserved - - - - - - - - (0x97) reserved - - - - - - - - (0x96) reserved - - - - - - - - (0x95) reserved - - - - - - - - (0x94) reserved - - - - - - - - (0x93) reserved - - - - - - - - (0x92) reserved - - - - - - - - (0x91) reserved - - - - - - - - (0x90) reserved - - - - - - - - (0x8f) reserved - - - - - - - - (0x8e) reserved - - - - - - - - (0x8d) reserved - - - - - - - - (0x8c) reserved - - - - - - - - (0x8b) ocr1bh timer/counter1 - output compare register b high byte 131 (0x8a) ocr1bl timer/counter1 - output compare register b low byte 131 (0x89) ocr1ah timer/counter1 - output compare register a high byte 131 (0x88) ocr1al timer/counter1 - output compare register a low byte 131 (0x87) icr1h timer/counter1 - input capture register high byte 132 (0x86) icr1l timer/counter1 - input capture register low byte 132 (0x85) tcnt1h timer/counter1 - counter register high byte 131 (0x84) tcnt1l timer/counter1 - counter register low byte 131 (0x83) reserved - - - - - - - - (0x82) tccr1c foc1a foc1b - - - - - -130 (0x81) tccr1b icnc1 ices1 - wgm13 wgm12 cs12 cs11 cs10 129 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 - - wgm11 wgm10 127 (0x7f) didr1 - - - - - -ain1dain0d 232 (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d 252 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
9 2593ls?avr?02/07 ATMEGA644 (0x7d) reserved - - - - - - - - (0x7c) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 248 (0x7b) adcsrb -acme - - - adts2 adts1 adts0 230 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 249 (0x79) adch adc data register high byte 251 (0x78) adcl adc data register low byte 251 (0x77) reserved - - - - - - - - (0x76) reserved - - - - - - - - (0x75) reserved - - - - - - - - (0x74) reserved - - - - - - - - (0x73) pcmsk3 pcint31 pcint30 pcint29 pcint28 pcint27 pcint26 pcint25 pcint24 66 (0x72) reserved - - - - - - - - (0x71) reserved - - - - - - - - (0x70) timsk2 - - - - - ocie2b ocie2a toie2 152 (0x6f) timsk1 - -icie1 - - ocie1b ocie1a toie1 132 (0x6e) timsk0 - - - - - ocie0b ocie0a toie0 104 (0x6d) pcmsk2 pcint23 pcint22 pcint21 pcint20 pcint19 pcint18 pcint17 pcint16 66 (0x6c) pcmsk1 pcint15 pcint14 pcint13 p cint12 pcint11 pcint10 pcint9 pcint8 66 (0x6b) pcmsk0 pcint7 pcint6 pcint5 pc int4 pcint3 pcint2 pcint1 pcint0 67 (0x6a) reserved - - - - - - - - (0x69) eicra - - isc21 isc20 isc11 isc10 isc01 isc00 63 (0x68) pcicr - - - - pcie3 pcie2 pcie1 pcie0 65 (0x67) reserved - - - - - - - - (0x66) osccal oscillator calibration register 34 (0x65) reserved - - - - - - - - (0x64) prr prtwi prtim2 prtim0 - prtim1 prspi prusart0 pradc 43 (0x63) reserved - - - - - - - - (0x62) reserved - - - - - - - - (0x61) clkpr clkpce - - - clkps3 clkps2 clkps1 clkps0 38 (0x60) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 55 0x3f (0x5f) sreg i t h s v n z c 11 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 11 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 11 0x3c (0x5c) reserved - - - - - - - - 0x3b (0x5b) reserved - - - - - - - - 0x3a (0x5a) reserved - - - - - - - - 0x39 (0x59) reserved - - - - - - - - 0x38 (0x58) reserved - - - - - - - - 0x37 (0x57) spmcsr spmie rwwsb sigrd rwwsre blbset pgwrt pgers spmen 274 0x36 (0x56) reserved - - - - - - - - 0x35 (0x55) mcucr jtd - -pud - - ivsel ivce 75/262 0x34 (0x54) mcusr - - - jtrf wdrf borf extrf porf 50/263 0x33 (0x53) smcr - - - - sm2 sm1 sm0 se 40 0x32 (0x52) reserved - - - - - - - - 0x31 (0x51) ocdr on-chip debug register 258 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 249 0x2f (0x4f) reserved - - - - - - - - 0x2e (0x4e) spdr spi 0 data register 162 0x2d (0x4d) spsr spif wcol - - - - - spi2x 162 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 160 0x2b (0x4b) gpior2 general purpose i/o register 2 26 0x2a (0x4a) gpior1 general purpose i/o register 1 26 0x29 (0x49) reserved - - - - - - - - 0x28 (0x48) ocr0b timer/counter0 output compare register b 104 0x27 (0x47) ocr0a timer/counter0 output compare register a 104 0x26 (0x46) tcnt0 timer/counter0 (8 bit) 104 0x25 (0x45) tccr0b foc0a foc0b - - wgm02 cs02 cs01 cs00 103 0x24 (0x44) tccr0a com0a1 com0a0 com0b1 com0b0 - - wgm01 wgm00 104 0x23 (0x43) gtccr tsm - - - - - psrasy psrsync 154 0x22 (0x42) eearh - - - - eeprom address register high byte 21 0x21 (0x41) eearl eeprom address register low byte 21 0x20 (0x40) eedr eeprom data register 21 0x1f (0x3f) eecr - - eepm1 eepm0 eerie eempe eepe eere 22 0x1e (0x3e) gpior0 general purpose i/o register 0 27 0x1d (0x3d) eimsk - - - - - int2 int1 int0 64 0x1c (0x3c) eifr - - - - - intf2 intf1 intf0 64 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
10 2593ls?avr?02/07 ATMEGA644 notes: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory address es should never be written. 2. i/o registers within the address range $00 - $1f are directly bit-accessible using th e sbi and cbi instructions. in these reg - isters, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag r ead as set, thus clearing the fl ag. the cbi and sbi instruction s work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses $00 - $3f must be used. when addressing i/o regis- ters as data space using ld and st instructions, $20 must be added to these addresses. the ATMEGA644 is a complex microcontroller with more peripheral units than can be suppor ted within the 64 location reserved in opcode for the in and out instructions. for the ext ended i/o space from $60 - $ff , only the st/sts/std and ld/lds/ldd instructions can be used. 0x1b (0x3b) pcifr - - - - pcif3 pcif2 pcif1 pcif0 65 0x1a (0x3a) reserved - - - - - - - - 0x19 (0x39) reserved - - - - - - - - 0x18 (0x38) reserved - - - - - - - - 0x17 (0x37) tifr2 - - - - -ocf2bocf2atov2 153 0x16 (0x36) tifr1 - -icf1 - - ocf1b ocf1a tov1 133 0x15 (0x35) tifr0 - - - - - ocf0b ocf0a tov0 105 0x14 (0x34) reserved - - - - - - - - 0x13 (0x33) reserved - - - - - - - - 0x12 (0x32) reserved - - - - - - - - 0x11 (0x31) reserved - - - - - - - - 0x10 (0x30) reserved - - - - - - - - 0x0f (0x2f) reserved - - - - - - - - 0x0e (0x2e) reserved - - - - - - - - 0x0d (0x2d) reserved - - - - - - - - 0x0c (0x2c) reserved - - - - - - - - 0x0b (0x2b) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 88 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 88 0x09 (0x29) pind pind7 pind6 pi nd5 pind4 pind3 pind2 pind1 pind0 88 0x08 (0x28) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 87 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 87 0x06 (0x26) pinc pinc7 pinc6 pi nc5 pinc4 pinc3 pinc2 pinc1 pinc0 88 0x05 (0x25) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 87 0x04 (0x24) ddrb ddb7 ddb6 ddb5 d db4 ddb3 ddb2 ddb1 ddb0 87 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 87 0x02 (0x22) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 87 0x01 (0x21) ddra dda7 dda6 dda5 d da4 dda3 dda2 dda1 dda0 87 0x00 (0x20) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 87 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
11 2593ls?avr?02/07 ATMEGA644 5. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc knone3 rcall k relative subroutine call pc pc + k + 1 none 4 icall indirect call to (z) pc znone4 call k direct subroutine call pc knone5 ret subroutine return pc stack none 5 reti interrupt return pc stack i 5 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2
12 2593ls?avr?02/07 ATMEGA644 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 elpm rd, z extended load program memory rd (z) none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 mnemonics operands description operation flags #clocks
13 2593ls?avr?02/07 ATMEGA644 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
14 2593ls?avr?02/07 ATMEGA644 6. ordering information 6.1 ATMEGA644 note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc see ?maximum speed vs. v cc ? on page 317 . speed (mhz) (3) power supply ordering code (2) package (1) operational range 10 1.8 - 5.5v ATMEGA644v-10au ATMEGA644v-10pu ATMEGA644v-10mu 44a 40p6 44m1 industrial (-40 o c to 85 o c) 20 2.7 - 5.5v ATMEGA644-20au ATMEGA644-20pu ATMEGA644-20mu 44a 40p6 44m1 industrial (-40 o c to 85 o c) package type 44a 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 40p6 40-pin, 0.600? wide, plastic dual inline package (pdip) 44m1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, quad flat no-lead/micro lead frame package (qfn/mlf)
15 2593ls?avr?02/07 ATMEGA644 7. packaging information 7.1 44a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44a, 44-lead, 10 x 10 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 44a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
16 2593ls?avr?02/07 ATMEGA644 7.2 40p6 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 40p6 , 40-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 40p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0o ~ 15o d e eb common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.826 a1 0.381 ? ? d 52.070 ? 52.578 note 2 e 15.240 ? 15.875 e1 13.462 ? 13.970 note 2 b 0.356 ? 0.559 b1 1.041 ? 1.651 l 3.048 ? 3.556 c 0.203 ? 0.381 eb 15.494 ? 17.526 e 2.540 typ notes: 1. this package conforms to jedec reference ms-011, variation ac. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
17 2593ls?avr?02/07 ATMEGA644 7.3 44m1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44m1 , 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, g 44m1 5/27/06 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 a3 0.25 ref b 0.18 0.23 0.30 d d2 5.00 5.20 5.40 6.90 7.00 7.10 6.90 7.00 7.10 e e2 5.00 5.20 5.40 e 0.50 bsc l 0.59 0.64 0.69 k 0.20 0.26 0.41 note: jedec standard mo-220, fig. 1 (saw singulation) vkkd-3. top view s ide view bottom view d e marked pin# 1 id e2 d2 b e pin #1 corner l a1 a3 a seating plane pin #1 triangle pin #1 chamfer (c 0.30) option a option b pin #1 notch (0.20 r) option c k k 1 2 3 5.20 mm exposed pad, micro lead frame package (mlf)
18 2593ls?avr?02/07 ATMEGA644 8. errata 8.1 rev. c inaccurate adc conversi on in differential mode with 200x gain . 1. inaccurate adc conver sion in differential mode with 200x gain with avcc < 3.6v, random conver sions will be inaccurate. typica l absolute accuracymay reach 64 lsb. problem fix/workaround none 8.2 rev. b not sampled 8.3 rev. a eeprom read from applicat ion code does not work in lock bit mode 3. 1. eeprom read from applic ation code does not work in lock bit mode 3 when the memory lock bits lb2 and lb1 are programmed to mode 3, eeprom read does not work from the application code. problem fix/work around do not set lock bit protection mode 3 when the application code needs to read from eeprom.
19 2593ls?avr?02/07 ATMEGA644 9. datasheet revision history please note that the referring page numbers in th is section are referred to this document. the referring revision in this section are referring to the document revision. 9.1 rev. 2593l - 02/07 9.2 rev. 2593k - 01/07 9.3 rev. 2593j - 09/06 9.4 rev. 2593i - 08/06 9.5 rev. 2593h - 07/06 1. updated table 24-7 on page 282 . 1 removed the ?not recommended in new designs? notice on page 1 . 2. updated figure 2-1 on page 3 . 3. updated ?pcifr ? pin change interrupt flag register? on page 65 . 4. updated table 21-4 on page 248 . 5. added note to ?dc characteristics? on page 315 . 1. updated ?calibrated internal rc oscillator? on page 34 . 2. updated ?fast pwm mode? on page 119 . 3. updated ?device identification register? on page 260 . 4. updated ?signature bytes? on page 286 . 5. updated table 13-3 on page 100 , table 13-6 on page 101 , table 14-3 on page 128 , table 14-4 on page 128 , table 14-5 on page 129 , table 15-3 on page 146 , table 15-6 on page 147 and table 15-8 on page 148 . 1. updated note in ?pin configurations? on page 2 . 2. updated table 7-2 on page 30 , table 12-11 on page 83 and table 24-7 on page 282 . 3. updated ?timer/counter prescaler? on page 154 . 1. updated ?fast pwm mode? on page 119 . 2. updated figure 14-7 on page 120 . 3. updated table 24-7 on page 282 . 4. updated ?packaging information? on page 360 .
20 2593ls?avr?02/07 ATMEGA644 9.6 rev. 2593g - 06/06 9.7 rev. 2593f - 04/06 9.8 rev. 2593e - 04/06 9.9 rev. 2593d - 04/06 9.10 rev. 2593c - 03/06 9.11 rev. 2593b - 03/06 1. updated ?calibrated internal rc oscillator? on page 34 . 2. updated ?osccal ? oscillator calibration register? on page 35 . 3. updated table 26-5 on page 323 . 1. updated typos. 2. updated ?adc noise reduction mode? on page 41 . 3. updated ?power-down mode? on page 41 . 1. updated ?calibrated internal rc oscillator? on page 34 . 1. updated ?bit 6 ? acbg: analog comparator bandgap select? on page 231 . 2. updated ?prescaling and conversion timing? on page 236 . 1. added ?not recommended in new designs?. 2. removed rampz? extended z-pointer register for elpm/spm from datasheet. 3. updated table 10-1 on page 57 . 4. updated code example in ?interrupt vectors in ATMEGA644? on page 57 . 5. updated ?setting the boot loader lock bits by spm? on page 278 . 6. updated ?register summary? on page 7 . 1. removed the occurancy of atmega164 and atmega324. 2. updated adresses in registers. 3. updated ?architectural overview? on page 9 . 4. updated sram sizes in ?sram data memory? on page 19 . 5. updated ?i/o memory? on page 26 . 6. updated ?prr ? power reduction register? on page 43 . 7. updated register bit discription in ?8-bit timer/counter register description? on page 145 . 8. updated note in ?overview of the twi module? on page 206 .
21 2593ls?avr?02/07 ATMEGA644 9.12 rev. 2593a-06/05 1. initial revision. 9. updated feauters in ?analog-to-digital converter? on page 233 . 10. changed name from ?sfior? to ?adcsrb? in ?starting a conversion? on page 235 , in ?bit 5 ? adate: adc auto tr igger enable? on page 250 and ?bit 7, 5:3 ? res: reserved bits? on page 251 . 11. updated ?signature bytes? on page 286 . 12. updated ?dc characteristics? on page 315 . 13. updated ?typical characteristics? on page 324 . 14. updated example in ?supply current of io modules? on page 329 . 15. updated ?register summary? on page 7 . 16. updated figure 6-2 on page 20 and figure 21-1 on page 234 . 17. updated ?errata? on page 18 . 18. updated table 9-1 on page 47 , table 9-4 on page 51 , table 10-1 on page 57 , table 23- 1 on page 260 , table 25-6 on page 286 , table 25-14 on page 298 , table 26-3 on page 320 , table 27-1 on page 329 , table 27-2 on page 330 .
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